Design Verification Engineer

Industry & Sector: Semiconductor / ASIC & SoC design and verification. We build complex digital IPs and full-chip RTL for high-performance embedded, connectivity, and compute applications—delivering silicon-ready verification environments, regression infrastructure, and release-quality verification sign-offs.

Primary Job Title: ASIC/SoC Design Verification Engineer

Location: India (On-site)

About The Opportunity

We are hiring a hands-on Design Verification Engineer to join a high-velocity ASIC/SoC verification team. You will create and execute verification plans, develop reusable UVM testbenches, automate regressions, and drive closure for functional coverage and verification sign-off for tapeout-quality RTL.

Role & Responsibilities

• Author and maintain UVM-based verification environments and testbenches for block and subsystem-level RTL verification.
• Design and implement constrained-random tests, assertions, directed tests, and functional coverage models to meet verification goals.
• Plan, run, and automate nightly/CI regressions; triage simulation failures and drive root-cause analysis to closure.
• Collaborate with RTL designers and firmware teams to identify corner cases, develop verification plans, and debug issues using waveform and trace tools.
• Integrate verification IPs, build verification harnesses for SoC-level verification, and support emulation or FPGA bring-up as required.
• Prepare verification metrics, coverage closure reports, and sign-off documentation for design milestones.
  
  

Skills & Qualifications

Must-Have (Technical skills)

• AMBA (AXI, APB, AHB) is mandatory
• PCIe protocol knowledge & working experience is highly desirable.
• SystemVerilog
• Universal Verification Methodology
• SystemVerilog Assertions
• Coverage-driven verification
• Constrained-random verification
• Synopsys VCS
• Mentor Questa
• Python scripting
  
  

Must-Have (Qualifications)

• Proven track record in RTL verification for ASIC/SoC projects and ownership of verification deliverables.
• Strong debugging experience with simulation waveforms, assertion failures, and regression results.
  
  

Preferred

• Formal verification experience (e.g., JasperGold)
• Hardware emulation or FPGA prototyping experience (e.g., Palladium, Veloce)
• Experience with coverage closure tooling and CI integration (Jenkins, GitLab CI)
  
  

Benefits & Culture Highlights

• Collaborative engineering culture with clear ownership and fast feedback cycles.
• Opportunities to work end-to-end on tapeout-quality projects and influence verification architecture.
• On-site, hands-on role with exposure to latest EDA flows and silicon bring-up activities.
  
  

To apply: Candidates based in India who can work on-site and bring strong hands-on verification experience are encouraged to apply through Viraaj HR Solutions. We prioritize engineers who combine practical verification skills with a discipline for automation and measurable coverage closure.

Skills: python scripting,design,systemverilog,amba,axi,verification